Turn on to enter physical PLL counter parameters instead of specifying a desired output clock frequency.ĭirect, external feedback, normal, source synchronous, zero delay buffer, or lvds The minimum and maximum value is dependent on the selected device. Specifies the input frequency for the input clock, refclk, in MHz. If you need a fractional PLL, you must use the fPLL Intel Arria 10/Cyclone 10 FPGA IP core. ![]() The only legal selection is Integer-N PLL. Specifies the mode used for the IOPLL IP core. Specifies the speed grade for targeted device. Intel ® Arria ® 10, Intel ® Cyclone ® 10 GX ![]() ![]() IOPLL IP Core Parameters - PLL Tab Parameter
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